? 2001 microchip technology inc. ds80089a-page 1 pic16c74a the pic16c74a (rev. a) parts you have received con- form functionally to the device data sheet (ds30390 e ), except for the anomalies described below. all the problems listed here will be addressed in future revisions of the pic16c74a silicon. 1. module: 8-bit a/d module if the analog port is configured so that all analog pins are digital inputs (pcfg2:pcfg0 = 11x ), then doing a conversion on any pin of the analog port will give a result of adres = 0xff. work around configure the pcfg2:pcfg0 bits to a value that has any pin of the analog port configured as an analog input (such as pcfg2:pcfg0 = 100 ). conversion on any pin of the analog port (analog or digital) will now convert as expected. 2. module: ccp (compare mode) the compare mode may not operate as expected when configuring the compare match to drive the i/o pin low (ccpxm<3:0> = 1001 ). when the ccp module is changed to compare output low (ccpxm<3:0> = 1001 ) from any other non-compare ccp mode, the i/o pin will immedi- ately be driven low, regardless of the state of the i/o data latch. the pin will remain low when the compare match occurs (see table 1). however, when the ccp module is changed to compare output high (ccpxm<3:0> = 1000 ) from any other ccp mode, the i/o pin will immediately be driven low, regardless of the state of the i/o data latch. the pin will be driven high when the compare match occurs. table 1: compare output low switching work around to have the i/o pin high until the compare match low occurs, force a compare match high to get the i/o pin into the high state, then reconfigure the compare match to force the i/o low when the com- pare condition occurs. ccp mode ccpxm<3:0> = i/o pin state change ccp to ccpxm<3:0> = 1001 1000 0xxx hll lll 1000 hh? ll? 1001 h?l l?l 101x hll lll 11xx hll lll pic16c74a rev. a silicon errata sheet
pic16c74a ds80089a-page 2 ? 2001 microchip technology inc. 3. module: ccp (compare mode) the special event trigger of the compare mode may not occur if both of the following conditions exist: an instruction, one cycle (t cy ) prior to a timer1/compare register match has literal data equal to the address of a ccp register being used. specific cases include: an instruction in the same cycle as a timer1/compare register match has an msb of ? 0 ? . the interrupt for the compare event will still be generated, but no special event trigger will occur. work around use the interrupt service routine instead of using the special event trigger to reset timer1 (and start an a/d conversion, if applicable). 4. module: ssp (spi mode) when the spi is using timer2/2 as the clock source, a shorter than expected sck pulse may occur on the first bit of the transmitted/received data (figure 1). figure 1: sck pulse variation using timer2/2 work around to avoid producing the short pulse, turn off timer2 and clear the tmr2 register, load the sspbuf with the data to transmit, and then turn timer2 back on. refer to example 1 for sample code. example 1: avoiding the initial short sck pulse 5. module: ssp module (i 2 c? mode) if the bus is active when the i 2 c mode is enabled, and the next 8 bits of data on the bus match the address of the device, then the ssp module will generate an acknowledge pulse. work around before enabling the i 2 c mode, ensure that the bus is not active. 6. module: timer0 the tmr0 register may increment when the wdt postscaler is switched to the timer0 prescaler. if tmr0 = ffh, this will cause tmr0 to overflow (setting t0if). work around follow the following sequence: a) read the 8-bit tmr0 register into the w register b) clear the tmr0 register c) assign wdt postscaler to timer0 d) write w register to tmr0 unit register literal data ccp1 ccpr1l 15h ccpr1h 16h ccp1con 17h ccp2 ccpr2l 1bh ccpr2h 1ch ccp2c0n 1dh sd0 sck write sspbuf bit0=1 bit1=0 bit2=1 . . . . bsf status, rp0 ;bank 1 loop btfss sspstat,bf ;data received? ;(xmit complete?) goto loop ;no bcf status, rp0 ;bank 0 movf sspbuf, w ;w = sspbuf movwf rxdata ;save in user ram movf txdata, w ;w = txdata bcf t2con, tmr2on ;timer2 off clr tmr2 ;clear timer2 movwf sspbuf ;xmit new data bsf t2con, tmr2on ;timer2 on
? 2001 microchip technology inc. ds80089a-page 3 pic16c74a 7. module: timer1 the timer1 value may unexpectedly increment if either the tmr1h, or the tmr1l register is writ- ten. if timer1 is on and then turned off, perform- ing any write instruction with tmr1h as the destination, may cause tmr1l to increment. example 2: tmr1l increment (case 1) example 3: tmr1l increment (case 2) if timer1 is on and then turned off when tmr1h:tmr1l = xx:ff, performing any write instruction with tmr1l as the destination may cause tmr1h to increment. example 4: tmr1h increment work around to preserve timer1 register values: a) read timer1 register values into ? shadow ? registers. b) perform any write instruction(s) on the shadow registers. c) write the shadow register values back into the timer1 registers. 8. module: usart when the usart (sci) is configured in asynchro- nous mode with the brgh bit set, a high number of receive errors may be experienced. for asyn- chronous receive operations, it is recommended that the usart be configured with the brgh bit cleared. bsf t1con, tmr1on : bcf t1con, tmr1on movf tmr1h, 1 tmr1 value before movf instruction: tmr1h:tmr1l = 3f:00 tmr1 value after movf instruction: tmr1h:tmr1l = 3f:01 bsf t1con, tmr1on : bcf t1con, tmr1on movf tmr1h, 1 tmr1 value before movf instruction: tmr1h:tmr1l = ff:ff tmr1 value after movf instruction: tmr1h:tmr1l = ff:00 bsf t1con, tmr1on bcf t1con, tmr1on clrf tmr1l tmr1 value before clrf instruction: tmr1h:tmr1l = ff:ff tmr1 value after clrf instruction: tmr1h:tmr1l = 00:00 (tmr1if is not set.)
pic16c74a ds80089a-page 4 ? 2001 microchip technology inc. clarifications/corrections to the data sheet: in the device data sheet (ds30390 e ), the following clarifications and corrections should be noted. 1. module: i/o ports the specification for the high voltage open drain i/o (parameter d150, the ra4 pin) cannot be met without possible long term reliability issues on that i/o pin. if a high voltage drive is required, use an external transistor that can support the required voltage. the new value is shown in table 1. table 1: dc specification changes from data sheet 2. module: 8-bit a/d the minimum a/d reference voltage (parameter a20) has been improved. the new value is shown in table 2. table 2: dc specification changes from data sheet param no. sym. characteristic new specification data sheet specification units min typ max min typ max d150 v od ra4 open drain high voltage ?? 10 ?? 14 v param no. sym. characteristic new specification data sheet specification units min typ max min typ max a20 v ref reference voltage 2.5* ? v dd + 0.3 v 3.0 ? v dd + 0.3 v v * this parameter is characterized but not tested.
? 2001 microchip technology inc. ds80089a-page 5 pic16c74a 3. module: ssp (spi tm mode timing specifications) the spi interface timings (parameters 71, 71a, 72, 72a, 73, and 73a) have been modified. the new values are shown in table 3. table 3: dc specification changes from data sheet 4. module: timer1 the operation of timer1 needs some clarification when the timer registers are written when the tmr1on bit is set. the internal clock signal that is the input to the tmr1 prescaler affects the incrementing of timer1 (tmr1h:tmr1l registers and the timer1 pres- caler). when the timer1 registers are not written, the timer1 will increment on the rising edge of the tmr1 increment clock. when the tmr1h and/or tmr1l registers are written while this clock is high, tmr1 will incre- ment on the next rising edge of this clock. when the tmr1h and/or tmr1l registers are written while this clock is low, tmr1 will not incre- ment on the next rising edge of this clock, but must first have a falling clock and the rising clock, for tmr1 to increment. figure 1 shows the two cases of writes to the tmr1h and/or tmr1l registers. due to the v ih and v il thresholds on the oscillator/clock pins, external timer1 oscillator components, and exter- nal clock frequency, the timer1 increment clock may not be of a 50% duty cycle. the tmr1 increment clock is out of phase of the t1oso/t1cki pin by a small propagation delay. figure 1: writes to timer1 (external clock/oscillator mode) param no. sym. characteristic new specification data sheet specification units min typ max min typ max 71 t sc h sck input high time (slave mode) continuous 1.25 t cy + 30 ns ?? t cy + 20 ns ?? ns 71a single byte (1) 40 ?? n.a. ns 72 t sc l sck input low time (slave mode) continuous 1.25 t cy + 30 ns ?? t cy + 20 ns ?? ns 72a single byte (1) 40 ?? n.a. ns 73a t b 2 b last clock edge of the byte1 to 1st clock edge of the byte2 (1) 1.5 t cy + 40 ns ?? n.a. ns * this parameter is characterized but not tested. note 1: specification 73a is only required if specifications 71a and 72a are used. tmr1 increment write to tmr1h tmr1h:tmr1l increments write to tmr1h tmr1h:tmr1l increments clock (input to prescaler) and/or tmr1l register(s) and/or tmr1l register(s)
pic16c74a ds80089a-page 6 ? 2001 microchip technology inc. 5. module: rc oscillator the table for rc oscillator frequencies in the device characterization section of the data sheet is incorrect. the correct characterization informa- tion is shown in table 4. table 4: rc oscillator frequencies characterization changes from data sheet 6. module: brown-out reset (bor) the levels specified for the bor module thresh- olds (parameter d005) have changed. the new values are shown in table 5. . c ext r ext correct characterization data current data sheet values average % variation average % variation 22 pf 5.1 k 3.55 mhz 9.63% 4.12 mhz 1.4% 10 k 1.99 mhz 10.53% 2.35 mhz 1.4% 100 k 221.9 khz 12.10% 268 khz 1.1% 100 pf 3.3 k 1.77 mhz 10.67% 1.80 mhz 1.0% 5.1 k 1.22 mhz 10.41% 1.27 mhz 1.0% 10 k 669.4 khz 10.92% 688 khz 1.2% 100 k 71.5 khz 11.21% 77.2 khz 1.0% 330 pf 3.3 k 625.1 khz 10.68% 707 khz 1.4% 5.1 k 428.5 khz 10.96% 501 khz 1.2% 10 k 231.9 khz 11.32% 269 khz 1.6% 100 k 24.4 khz 12.93% 28.3 khz 1.1% the percentage variation indicated here is part-to-part variation due to normal process distribution. the variation indicated is 3 standard deviation from the average value for v dd = 5v. table 5: minimum and maximum bor reset voltages param no. sym. characteristic new specification data sheet specification units min typ max min typ max d005 v bor brown-out reset voltage 3.65 ? 4.35 3.70 ? 4.30 v
? 2001 microchip technology inc. ds80089a - page 7 ? all rights reserved. copyright ? 2001, microchip technology incorporated, usa. information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. no rep- resentation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accu- racy or use of such information, or infringement of patents or other intellectual property rights arising from such use or oth- erwise. use of microchip ? s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. the microchip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and other countries. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. no licenses are conveyed, implicitly or otherwise, under any intellectual prop- erty rights. ? trademarks the microchip name, logo, pic, picmicro, picmaster, pic- start, pro mate, k ee l oq , seeval, mplab and the embedded control solutions company are registered trade- marks of microchip technology incorporated in the u.s.a. and other countries. total endurance, icsp, in-circuit serial programming, filter- lab, mxdev, microid, flex rom, fuzzy lab, mpasm, mplink, mplib, picdem, icepic, migratable memory, fansense, economonitor, selectmode and microport are trademarks of microchip technology incorporated in the u.s.a. serialized quick term programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2001, microchip technology incorporated, printed in the u.s.a., all rights reserved. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified.
information contained in this publication regarding device applications and the like is intended through suggestion only and ma y be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warrant y is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patent s or other intellectual property rights arising from such use or otherwise. use of microchip ? s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellec- tual property rights. the microchip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and othe r countries. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. ds80089a-page 8 ? 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